1. Field of Invention
The present invention relates to a semiconductor memory device which accesses a memory cell in synchronization with a clock signal. In particular, the invention relates to a semiconductor memory device that improves the operating speed when successively performing data read-out followed by data write-in at the same address.
2. Description of Related Art
In order to realize high speed data accessing, various technologies in random accessible semiconductor devices (random access memory: hereafter RAM) have attracted public attention. High speed data transfer modes such as a high speed page mode and burst mode have been used.
Here, FIG. 12 is a timing chart which shows the operation of the RAM of a first prior art example.
This RAM reads-in the write-in signal WE* and the address signal ADR at the rise of the clock signal CLK. Further, when the write-in signal WE* is a write mode in an L state, the write-in data signal DI is taken-in at the rise.
Moreover, the "*" of WE*, row address strobe signal RAS* and column address strobe signal CAS*, which will be described hereafter, shows that the signal is negative logic.
Furthermore, in the timing chart of FIG. 12 and other figures, "invalid" shows that the read-out data signal DO is being renewed, and that the logic state is in a process of changing. Moreover, "valid" shows that the read-out data signal DO is established after the renewal. Further, concerning RAS*, CAS*, WE* and other input signals, or internal signals in the RAM, the broken line portions and the slanted line portions show that neither the H nor the L logic states influence the operating state in the operation of the RAM. Furthermore, the numbers which are numbered on the clock signal CLK of the timing chart are numbers for convenience of explanation which is performed using the timing chart. For example, "0" is a pulse 0, "1" is a pulse 1.
In FIG. 12 of the prior art, at the pulses 1, 3 and 5, at the time of each rise, the write-in signal WE* is in the H state, and the read mode is set, and the read-out access is performed. Moreover, at the pulses 2 and 4, the write mode is set, and the write access is performed.
FIG. 13 is a block diagram which shows the structure of the main parts of the RAM of a second prior art.
This prior art example has a control block 20B as shown in FIG. 13, and performs row selection in accordance with row address RA through a row decoder 12 and a row driver RD, then selects a column based on column address CA through a column decoder 14 and a column selecting circuit DS, and selects a memory cell MC in the memory cell array 10. Further, the symbol SCK of FIG. 13 shows a system clock, and an internal clock signal CLK is created based on the system clock.
When performing read-out access with respect to the selected memory cell MC, a data read-out circuit 44 is used. On the other hand, when performing write-in access, a data write-in circuit 46 and input data latch circuit 48 are used. Further, in both the read-out access and the write-in access, the bit line equalizing circuit 11 and data equalizing circuit 15, which perform equalization and pre-charge of the bit line are used. In FIG. 13, the symbol SA shows a sense amplifier.
Next, the control block 20B, as shown as FIG. 14b, is composed of an operation control circuit 22B, a clock buffer 24, an address buffer 26, a row address buffer 27 and a column address buffer 28. Moreover, the above-mentioned operation control circuit 22B is composed of an operation mode judgment circuit, of which the entire internal circuit structure is shown in FIG. 15, a read-out control circuit, which is shown in FIG. 16, and a write-in control circuit, which is shown in FIG. 17. The control block 20B thus structured creates and outputs each signal that is shown at the right of FIG. 14a based on each signal which is input from the left side in FIG. 14a.
Here, the aforementioned operation mode judgment circuit is explained by using FIG. 15. The row address strobe signal RAS*, the column address strobe signal CAS* and the write-in signal WE* are taken-in to flip flops FF 10.about.FF12 in synchronization with the clock signal CLK. In response to the various signals which are taken-in, a column selection signal CSEL is created using logic gates G10, G11 and G14 and delay circuits D11 and D12. Moreover, the read mode signal READ is created by using the logic gates G10 and G12, and the write mode signal WRITE is created using the logic gates G10 and G13.
Next, FIG. 18 is a timing chart which shows the operation of the RAM of this second prior art.
A high speed page mode is provided in this prior art. Thus, the prior art takes-in the row address signal ADX and performs the row address selection, and then the column address ADY is taken-in, and the column address selection is performed at the third pulse of the clock signal CLK. Next, at the rise of the clock signal CLK of this embodiment, it is determined whether the row address read-in will be performed, when the read mode will be set, and whether the write mode will be set, in accordance with the row address strobe signal RAS*, the column address strobe signal CAS*, and the write-in signal WE*, as shown in FIG. 14c.
For example, as shown in FIG. 18, pulse 1 to pulse 9 of the clock signal CLK indicate access to the address of the same page, thus, a high speed page mode is used.
First, the row address is read-in at pulse 1, then the row address is selected at the pulse 1 and pulse 2.
Moreover, at the pulses 3, 5, 7 and 9, the read mode is set at each rise of the clock pulse, and the read-out access is performed. During read-out access, not only is the read mode set at the rise of the clock signal CLK, but the taking-in of the column address ADY is also performed. After this, as shown at "invalid" in the figure, the read-out data signal DO is changed through the memory cell access in accordance with the column address signal ADY, after which the read-out data signal DO is set as shown at "valid" in the figure.
At pulses 4, 6 and 8, the write mode is set at each rise of the pulse, and write-in access is performed. By this write-in access, at the rises of the clock signal CLK, the write mode is set and the column address signal ADY is taken-in, and further, the write-in data signal DI is taken-in. The write-in data signal DI thus read-in is written-into the memory cell which is indicated by the column address signal ADY during one cycle of the clock signal CLK.
FIG. 11a is a timing chart which shows the operation of prior art which includes the aforementioned first prior art and second prior art.
In this FIG. 11a, "the operation mode signal" as in the first prior art, is a signal for setting the read mode or the write mode in the RAM (hereafter called the first prior art RAM) which takes-in an address during one cycle of the clock signal CLK without distinguishing between the row address and column address. Or, as in the second prior art, in a RAM (hereafter called the second prior art RAM) which, after taking in the row address strobe signal RAS* during one or more clock pulses, then performs the read-out access or the write-in access while reading in a column address strobe signal CAS* during a pulse cycle of a separate clock signal CLK, it is a signal which reads-in the row address and sets a memory operation mode such as the read mode or the write mode.
Accordingly, the row address strobe signal RAS*, the column address strobe signal CAS*, and the write-in signal WE* are included in this operation mode signal of the aforementioned first prior art or second prior art.
The read-out access operation is explained in FIG. 11a.
A1 (operation mode judgment): evaluate the operation mode in accordance with the operation mode signal.
A2 (address selection): perform an address selection. A row address and a column address selection are performed in the first prior art RAM. As for the second prior art RAM, only the column address selection is performed here, since the row address already has been selected during a previous clock signal CLK.
A3 (sense amp operation): perform read-out of the data in the selected memory cell using a data line and a sense amp.
A4 (output latch): temporarily store the output of the sense amp in the output data latch circuit, then perform an operation which outputs the signal from the RAM.
C1 (release the address selection): in the first prior art RAM, the selection of the row address and the column address are released. Or, in the second prior art RAM, the selection of the column address is released.
C2 (equalize and pre-charge): perform equalizing and pre-charging of the data line (or perform equalizing and pre-charging of the data line and the bit line).
Next, in FIG. 11a, the operations of the write-in access are explained in order.
B1 (operation mode judgment): evaluate a write mode in accordance with the operation mode signal.
B2 (address selection): perform selection of the row address and the column address in the first prior art RAM. Or in the second prior art, the row address already has been selected during a prior clock signal CLK, so only the column address selection is performed.
B3 (memory cell write-in operation): perform the actual write-in operation of the write-in data inputted into the memory cell whose address is selected.
C1 (release the address selection): same as C1 of the read-out access.
C2 (equalize and pre-charge): same as C2 of the read-out access.
In both the first prior art and the second prior art, the read-out access and the write-in access are independent operation cycles, each requiring operation mode judgment and the address selection. When using the RAM with respect to the same address memory cell, there are cases when the write-in access is performed after performing the read-out access. In this case, both the first prior art and the second prior art need 2 pulses (2 clocks) of the clock signal CLK.
Here, when performing the read-out access and the write-in access in this order into a memory cell of the same address, it is sufficient to just use the former operation mode judgment and the former address selection, and the operation mode judgment and the address selection for write-in access is repeated.
For example, in the first prior art as shown in FIG. 12, the time from t1 to t2 is the period to perform the word line selection completion processing, the column address selection completion processing, and pre-charging and equalizing of the bit line and the data line, and the like. Moreover, the time from t2 to t3 is the period to perform the address decoding, word line selection and column address selection. These two periods become redundant when successively performed for read-out access and write-in access with respect to the same memory cell.
Moreover, in the second prior art as shown in FIG. 18, the time t1 to t2 is the period to perform the column address completion processing, pre-charge and equalization of the data line, and the like. Moreover, from the time t2 to t3 is the period to perform the column address decoding and the column address selection. These periods become redundant when performing read-out access and write-in access successively, and the operating speed becomes lower.
The present invention solves these prior problems, and has an object of providing a semiconductor memory device which improves the operating speed when performing successive read-out and write-in at the same address. Moreover, it has an object of providing an integrated circuit or electronic system which includes this kind of semiconductor memory device as a component thereof.